In the field of bipolar transistor devices it is generally recognized that it is desirable to incorporate complementary transistors, i.e. both NPN and PNP type transistors, onto a single chip or substrate. When complementary transistors are thus employed, in operation one type of transistor is typically on while the other type is off, both types changing on/off states relatively simultaneously. This complementary operation results in improved semiconductor chip characteristics, such as decreased power consumption and decreased signal noise.
However, it is also recognized that it is difficult to fabricate high-performance complementary transistors on a single substrate. This difficulty is due in large part to the fact that the fabrication of high-performance transistors requires a highly specialized process, and such a process is typically tailored to either the NPN or PNP type of transistor. In the past it has been extremely difficult to provide a fabrication process which yields high-performance transistors of both the NPN and PNP types on a single substrate/chip.
Those skilled in the art have addressed the task of fabricating complementary bipolar transistors in many different manners, several of which are briefly described below.
U.S. Pat. No. 4,719,185 to Goth (assigned to the assignee of the present invention) shows a complementary transistor structure wherein vertical NPN and PNP transistors are formed by ion implantation of the transistor regions. Metal contacts are subsequently provided to the transistor regions.
U.S. Pat. No. 4,485,552 to Magdo et al. (assigned to the assignee of the present invention) shows a complementary transistor structure utilizing isolation structures that permit carefully controlled impurity doping of the transistor regions. The extrinsic base region and the emitter region of the PNP device are out-diffused from doped polysilicon regions.
U.S. Pat. No. 3,730,786 to Ghosh (assigned to the assignee of the present invention) shows a method for forming complementary bipolar transistors wherein a vertical NPN emitter region and a vertical PNP base region are formed by out-diffusion from a single doped oxide layer. The NPN base region and the PNP emitter region are formed by separate diffusions.
European Patent Application 0 301 468 by Fairchild Semiconductor Corporation shows a process for fabricating complementary bipolar transistors wherein the emitter and extrinsic base regions of the complementary transistors are formed by out-diffusion from a single layer of polysilicon. This out-diffusion is performed by first defining and doping selected regions of the polysilicon layer, and then by heating the device to out-diffuse these regions into the substrate. The separation of the emitter and extrinsic base is limited by lithographic resolution of the type used to etch the polysilicon therebetween.
The present invention is directed to providing a method for fabricating high performance, complementary bipolar transistors utilizing a process compatible with current self-aligned transistor fabrication technology.